HPC is already starting to suffer from the exhaustion of traditional Moore’s Law scaling as we know it and have come to rely upon it for clockwork performance improvements for almost 50 years. There have been numerous near-misses in the past as the semiconductor industry approached the limits of one or another silicon processing technology, but this time we are reaching the fundamental limits of CMOS itself and the alternatives that would rescue us from a performance plateau have already missed their cue. This talk will explore the dimensions of the problem, focus on the degrees of freedom we retain to push CMOS to its ultimate limits, and sketch the technology and architecture advances — and their implications for users and their codes -- that are already supporting us through the crisis.


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